This invention relates, in general, to semiconductor devices and, more particularly, to over voltage protection structures and methods of integration into a semiconductor device to achieve high avalanche voltage protection capabilities.
In the past, semiconductor devices have been exposed to potentially destructive voltages and currents during normal operation. Such conditions are commonly encountered in the application of power semiconductor devices such as MOSFETs, BJTs, and IGBTs. For example, a semiconductor power device such as a power MOSFET, is frequently used to switch inductive loads in a circuit. When the power MOSFET is switched off, the energy stored in the inductor will force the drain voltage of the power MOSFET to rise rapidly above the supply voltage. If no limiting means are employed, this rise will continue until the drain-source avalanche voltage of the power MOSFET is reached, whereupon the energy stored in the inductor will be dissipated in the power MOSFET during device avalanche resulting in stress-induced failure of the power MOSFET.
Various processing techniques are commonly employed to reduce the internal parasitic elements of a power MOSFET thus making it less susceptible to avalanche-stress induced failure. A problem with relying on process modifications is that normal variations in the processing parameters of a power MOSFET may inhibit the optimization or reduce the effectiveness of these techniques.
Other methods of protection involve the application of external devices to render the power MOSFET less susceptible to avalanche stress. One such method involves the deployment of a drain-source clamp diode: an external diode connected between the drain and source of the power MOSFET, whose avalanche voltage is less than that of the power MOSFET. When the rising drain-source voltage reaches the avalanche voltage of the drain-source clamp diode, the energy stored in the inductor is dissipated in the drain-source clamp diode rather than the power MOSFET. The amount of energy that can be safely dissipated in this fashion depends on the dissipation capability of the drain-source clamp diode. Large amounts of energy may require numerous clamp diodes. It should be noted that in the above-mentioned technique that while the drain-source clamp diode is dissipating the inductive energy, the power MOSFET is idle.
A more advantageous method of protection involves diverting a small fraction of the inductive energy to the power MOSFET gate by means of a drain-gate clamp diode whose avalanche voltage is less than the avalanche voltage of the power MOSFET. A suitable gate-source termination resistor is also employed in this method. When the rising drain voltage reaches the avalanche voltage of the drain-gate clamp diode, the resulting avalanche current develops a voltage across the gate-source termination resistor which turns on the power MOSFET, effectively clamping its drain voltage to the sum of the drain-gate diode avalanche voltage and the voltage across the gate-source termination resistor. In this method the power MOSFET acts as its own clamp, and dissipates the inductive energy in the less stressful conduction mode. It is customary to add a second blocking diode in back-to-back configuration with the drain-gate clamp diode to enable the gate-source voltage in normal operation to exceed the drain-source voltage.
An advantage of using a drain-gate clamp over using a drain-source clamp is that the drain-gate diode, blocking diode, and gate-source termination resistor only need to handle enough energy to charge the power MOSFET input capacitances and therefore may be small in size and cost.
A disadvantage of these external clamp methods is that additional parts are needed to protect the power MOSFET, thus increasing the cost of the total system. In addition, the physical layout of some applications may preclude placing the clamp circuitry in close proximity to the power MOSFET. The resulting parasitic inductances act as impedances that slow the response time of the clamp circuitry. Therefore the power MOSFET may have to endure some avalanche stress until the clamps become active. It would be advantageous to provide a means of protecting the power MOSFET that achieves intimate proximity to the power MOSFET and does not increase the number of additional system components.
One single chip solution was taught in U.S. Pat. No. 5,365,099 issued on Nov. 15, 1994. In this patent, a plurality of back to back polysilicon diodes are used to limit the voltage potential that may arise between the gate and drain terminal. These diodes not only protect the device, but provide the added feature of doing so with a temperature compensated sustaining voltage. This solution is limited, however, to applications where the maximum avalanche voltage the MOSFET will be exposed to is 400 volts. Increasing the number of poly diodes will ultimately maximize the blocking voltage a semiconductor device can support. There are physical and performance limitations that do not provide protection for higher voltage MOSFET devices with blocking voltages above 800 volts.
In an effort to break the 500 volt barrier, it has been suggested in the literature, publication by Yamazaki from the 1993 International Symposium on Power Semiconductor Devices and ICs pages 41-45, that an avalanche diode structure can be built in conjunction with the MOSFET device using P-N junctions. The junctions can be fabricated along with the device with no added expense or processing steps. These structures can provide the protection necessary to survive voltage spikes in excess of 1000 volts, however the circular nature of these implanted avalanche junctions makes it extremely difficult to reproduce avalanche diodes with consistent avalanching characteristics. It is also not possible to achieve optimal MOSFET device performance and optimize the desired voltage protection without either sacrificing MOSFET performance or introducing variability in the voltage range that the avalanche diode will operate.
By now, it should be appreciated that it would be advantageous to provide an improved method of protecting a semiconductor device from avalanche stress at voltages in excess of 500 volts, but it should also be a single chip solution that is easy and efficient to manufacture without impeding the MOSFET performance.